Researchers at the Massachusetts Institute of Technology (MIT) have developed a new scalable superconducting memory array that significantly reduces error rates. Published on January 25, 2026, in the journal Nature Electronics, this advancement may enhance the efficiency of quantum computers by providing faster and more energy-efficient memory components.
Superconducting memory devices are made from materials that conduct electricity without resistance when cooled below a certain temperature. These devices promise faster performance and lower energy consumption compared to traditional memory technologies. However, existing superconducting memories have struggled with high error rates and scaling challenges, limiting their practical application.
The team at MIT has created a superconducting memory based on nanowires—one-dimensional structures known for their unique optoelectronic properties. As outlined in their study, the new 4 × 4 superconducting nanowire memory array is designed for scalable row-column operations with a functional density of 2.6 Mbit cm −2. The researchers noted, “Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers.”
Each memory cell in this array consists of a superconducting nanowire loop with two temperature-dependent switches and a variable kinetic inductor. The kinetic inductor plays a crucial role by resisting changes in electrical current, which supports the stable operation of the memory. The researchers explained, “The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out.”
To write and read information, the memory utilizes precisely timed electrical pulses sent to specific cells. These pulses briefly heat one of the nanowire switches, increasing its resistance and injecting a magnetic flux into the loop. This magnetic flux encodes data values of either 0 or 1. Once the pulse ceases, the nanowire cools, returning to its superconducting state and trapping the information.
In preliminary tests, the new memory array demonstrated impressive performance, achieving an error rate of approximately 1 in 100,000 operations. This rate is significantly lower than that of many superconducting memories developed in recent years. The authors stated, “We achieve a minimum bit error rate of 10 −5.” They also utilized circuit-level simulations to explore the memory cell’s dynamics and performance limits under varying conditions.
The findings from this research indicate a promising step towards the practical deployment of superconducting memory systems. With further refinement and scaling, the design could pave the way for more reliable and high-performing memory systems in quantum computing and beyond.
This article has been prepared by Ingrid Fadelli, edited by Lisa Lock, and reviewed by Robert Egan. The content is a product of careful research and fact-checking to uphold journalistic integrity.
